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Comparative Analysis Of Different AES Implementation Techniques For Efficient Resource Usage And Better Performance Of An FPGA

المصدر: مجلة جامعة الملك سعود - علوم الحاسب والمعلومات
الناشر: جامعة الملك سعود
المؤلف الرئيسي: Farooq, Umer (Author)
مؤلفين آخرين: Aslam, M. Faisal (Co-Author)
المجلد/العدد: مج29, ع3
محكمة: نعم
الدولة: السعودية
التاريخ الميلادي: 2017
الصفحات: 295 - 302
DOI: 10.33948/0584-029-003-006
ISSN: 1319-1578
رقم MD: 974190
نوع المحتوى: بحوث ومقالات
اللغة: الإنجليزية
قواعد المعلومات: science
مواضيع:
كلمات المؤلف المفتاحية:
Cryptography | Embedded Security | AES | FPGA | Exploration
رابط المحتوى:
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المستخلص: Over the past few years, cryptographic algorithms have become increasingly important. Advanced Encryption Standard (AES) algorithm was introduced in early 2000. It is widely adopted because of its easy implementation and robust security. In this work, AES is implemented on FPGA using five different techniques. These techniques are based on optimized implementation of AES on FPGA by making efficient resource usage of the target device. Experimental results obtained are quite varying in nature. They range from smallest (suitable for area critical application) to fastest (suitable for performance critical applications) implementation. Finally, technique making efficient usage of resources leads to frequency of 886.64 MHz and throughput of 113.5 Gb/s with moderate resource consumption on a Spartan-6 device. Furthermore, comparison between proposed technique and existing work shows that our technique has 32% higher frequency, while consuming 2.63_ more slice LUTs, 8.33_ less slice registers, and 12.59_ less LUT-FF pairs.

ISSN: 1319-1578

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