A High Level Implementation And Performance Evaluation Of Level-I Asynchronous Cache On FPGA
| المصدر: | مجلة جامعة الملك سعود - علوم الحاسب والمعلومات |
|---|---|
| الناشر: | جامعة الملك سعود |
| المؤلف الرئيسي: | Jhamb, Mansi (Author) |
| مؤلفين آخرين: | Sharma, Ravi K. (Co-Author) , Gupta, A. K. (Co-Author) |
| المجلد/العدد: | مج29, ع3 |
| محكمة: | نعم |
| الدولة: |
السعودية |
| التاريخ الميلادي: |
2017
|
| الصفحات: | 410 - 425 |
| DOI: |
10.33948/0584-029-003-014 |
| ISSN: |
1319-1578 |
| رقم MD: | 974229 |
| نوع المحتوى: | بحوث ومقالات |
| اللغة: | الإنجليزية |
| قواعد المعلومات: | science |
| مواضيع: | |
| كلمات المؤلف المفتاحية: |
Asynchronous | Handshaking | Cache
|
| رابط المحتوى: |
| المستخلص: |
To bridge the ever-increasing performance gap between the processor and the main memory in a cost-effective manner, novel cache designs and implementations are indispensable. Cache is responsible for a major part of energy consumption (approx. 50%) of processors. This paper presents a high level implementation of a micropipelined asynchronous architecture of L1 cache. Due to the fact that each cache memory implementation is time consuming and errorprone process, a synthesizable and a configurable model proves out to be of immense help as it aids in generating a range of caches in a reproducible and quick fashion. The micropipelined cache, implemented using C-Elements acts as a distributed message-passing system. The RTL cache model implemented in this paper, comprising of data and instruction caches has a wide array of configurable parameters. In addition to timing robustness our implementation has high average cache throughput and low latency. The implemented architecture comprises of two direct-mapped, write-through caches for data and instruction. The architecture is implemented in a Field Programmable Gate Array (FPGA) chip using Very High Speed Integrated Circuit Hardware Description Language (VHSIC HDL) along with advanced synthesis and place and-route tools. |
|---|---|
| ISSN: |
1319-1578 |
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